Nonvolatile semiconductor memory device

ABSTRACT

A nonvolatile semiconductor memory device includes a first dielectric layer formed on the major surface of a semiconductor substrate, a floating gate electrode layer formed on the first dielectric layer, a second dielectric layer obtained by sequentially forming, on the floating gate electrode layer, a lower dielectric film mainly containing silicon and nitrogen, an intermediate dielectric film, and an upper dielectric film mainly containing silicon and nitrogen, a control gate electrode layer formed on the second dielectric layer, and a buried dielectric layer formed by covering the two side surfaces in the gate width direction of the stacked structure including the above-mentioned layers. The nonvolatile semiconductor memory device further includes a silicon oxide film formed near the buried dielectric layer in the interface between the floating gate electrode layer and lower dielectric film.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromprior Japanese Patent Application No. 2006-118272, filed Apr. 21, 2006,the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a nonvolatile semiconductor memorydevice and, more particularly, to a nonvolatile semiconductor memorydevice having a multilayered oxide and nitride film.

2. Description of the Related Art

Micropatterning of nonvolatile semiconductor memory elements poses theproblem of an increase in interference between adjacent cells. Thismakes it necessary to decrease the thickness of a multilayered oxide andnitride film used as an interelectrode dielectric film. In addition, toreduce a leakage current that flows through the interelectrodedielectric film when its thickness decreases, a multilayered oxide andnitride film having nitride films in the upper and lower interfaces isalready proposed.

In an dielectric film having oxide films in the upper and lowerinterfaces, it is possible by post oxidation after cell processing toreduce a leakage current caused by the damage during the processing, anda leakage current caused by a pointed end face of an electrode layer(e.g., Jpn. Pat. Appln. KOKAI Publication No. 2003-31705).

Unfortunately, in an interelectrode dielectric film having nitride filmsin the upper and lower interfaces (e.g., U.S. Pat. No. 5,661,056), theinfluences of the leakage current caused by the damage during theprocessing and the leakage current caused by the acute-angled electrodeend face remain.

BRIEF SUMMARY OF THE INVENTION

According to a first aspect of the present invention, there is provideda nonvolatile semiconductor memory device comprising: a first dielectriclayer formed on a major surface of a semiconductor substrate; a floatinggate electrode layer formed on the first dielectric layer; a seconddielectric layer obtained by sequentially forming, on the floating gateelectrode layer, a lower dielectric film mainly containing silicon andnitrogen, an intermediate dielectric film, and an upper dielectric filmmainly containing silicon and nitrogen; a control gate electrode layerformed on the second dielectric layer; a buried dielectric layer formedby covering two side surfaces in a gate width direction of a stackedstructure including the first dielectric layer, the floating gateelectrode layer, the second dielectric layer, and the control gateelectrode layer; and a silicon oxide film formed near the burieddielectric layer in an interface between the floating gate electrodelayer and the lower dielectric film.

According to a second aspect of the present invention, there is provideda nonvolatile semiconductor memory device comprising: a first dielectriclayer formed on a major surface of a semiconductor substrate; a floatinggate electrode layer formed on the first dielectric layer; a seconddielectric layer obtained by sequentially forming, on the floating gateelectrode layer, a lower dielectric film mainly containing silicon andnitrogen, an intermediate dielectric film, and an upper dielectric filmmainly containing silicon and nitrogen; a control gate electrode layerformed on the second dielectric layer; a buried dielectric layer formedby covering two side surfaces in a gate width direction of a stackedstructure including the first dielectric layer, the floating gateelectrode layer, the second dielectric layer, and the control gateelectrode layer; and a silicon oxide film formed near the burieddielectric layer in an interface between the control gate electrodelayer and the upper dielectric film.

According to a third aspect of the present invention, there is provideda nonvolatile semiconductor memory device fabrication method comprising:forming a first dielectric layer on a major surface of a semiconductorsubstrate; forming a floating gate electrode layer on the firstdielectric layer; etching two side surfaces in a gate length directionof each of the floating gate electrode layer and the first dielectriclayer; covering, with an dielectric film, the two side surfaces in thegate length direction of the first dielectric layer and at leastportions of the two side surfaces in the gate length direction of thefloating gate electrode layer, thereby forming a buried dielectric layerhaving an upper surface positioned between an upper surface and a bottomsurface of the floating gate electrode layer; forming a seconddielectric layer on the floating gate electrode layer and the burieddielectric layer, comprising: forming a lower dielectric film mainlycontaining silicon and nitrogen; forming an intermediate dielectric filmon the lower dielectric film; and forming an upper dielectric filmmainly containing silicon and nitrogen on the intermediate dielectricfilm; forming a control gate electrode layer on the second dielectriclayer; etching two side surfaces in a gate width direction of each ofthe first dielectric layer, the floating gate electrode layer, thesecond dielectric layer, and the control gate electrode layer, therebyforming isolation trenches; and forming, by oxidation, a first siliconoxide film near the isolation trench in an interface between thefloating gate electrode layer and the lower dielectric film, and asecond silicon oxide film near the isolation trench in an interfacebetween the control gate electrode layer and the upper dielectric film.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 is a sectional view showing a fabrication step of a nonvolatilesemiconductor memory device according to the first embodiment;

FIG. 2 is a sectional view showing a nonvolatile semiconductor memorydevice fabrication step that follows FIG. 1;

FIG. 3 is a sectional view showing a nonvolatile semiconductor memorydevice fabrication step that follows FIG. 2;

FIG. 4 is a sectional view showing a nonvolatile semiconductor memorydevice fabrication step that follows FIG. 3;

FIG. 5 is a sectional view showing a nonvolatile semiconductor memorydevice fabrication step that follows FIG. 4;

FIG. 6 is a sectional view showing a nonvolatile semiconductor memorydevice fabrication step that follows FIG. 5;

FIG. 7 is a sectional view taken along a line A-A′ in FIG. 6 and showinga nonvolatile semiconductor memory device fabrication step that followsFIG. 6;

FIG. 8 is a sectional view showing a nonvolatile semiconductor memorydevice fabrication step that follows FIG. 7;

FIG. 9 is a sectional view showing the nonvolatile semiconductor memorydevice according to the first and second embodiments;

FIG. 10 is a graph showing the current densities of leakage currentsthat flow through an interelectrode dielectric film when interface oxidefilms are formed and no interface oxide films are formed;

FIG. 11 is a sectional view showing a fabrication step, that followsFIG. 7, of a nonvolatile semiconductor memory device according to thethird embodiment;

FIG. 12 is a sectional view showing a nonvolatile semiconductor memorydevice fabrication step that follows FIG. 11; and

FIG. 13 is a sectional view showing the nonvolatile semiconductor memorydevice according to the third embodiment.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention will be explained in detail belowwith reference to the accompanying drawing. Note that in the followingexplanation, the same reference numerals denote elements having the samefunctions.

First Embodiment

FIGS. 1 to 8 are views showing fabrication steps of a nonvolatilesemiconductor memory device according to the first embodiment of thepresent invention.

As shown in the sectional view of FIG. 1, a tunnel dielectric film 2(first dielectric layer) about 1- to 15-nm-thick is first formed on themajor surface of a p-type silicon substrate (or an n-type siliconsubstrate having a p-type well) 1. The tunnel dielectric film 2 is madeof, e.g., a silicon thermal oxide film, a silicon nitride film, or astacked film of these films.

On the tunnel dielectric film 2, a floating gate electrode layer 3 about10- to 200-nm-thick made of polysilicon or the like is formed bychemical vapor deposition (CVD). The floating gate electrode layer 3functions as a charge storage layer of a memory cell. Then, a siliconnitride film 4 about 50- to 200-nm-thick is formed by CVD. In addition,a silicon oxide film 5 about 50- to 400-nm-thick is formed by CVD. Thesilicon oxide film 5 is coated with a photoresist 6. The structure shownin FIG. 1 is obtained by patterning the photoresist 6 by patternexposure.

After that, the silicon oxide film 5 is etched by using the photoresist6 shown in FIG. 1 as an anti-etching mask. The photoresist 6 is removedafter the etching, and the silicon nitride film 4 is then etched byusing the silicon oxide film 5 as a mask. In addition, the floating gateelectrode layer 3, dielectric film 2, and silicon substrate 1 aresequentially etched to form trenches for isolation as shown in FIG. 2.

After that, a high-temperature post oxidation step is performed toremove the damage from the section formed by the etching. Subsequently,a 200- to 1,500-nm-thick buried dielectric film 7 such as a siliconoxide film is formed and buried in the isolation trenches. Furthermore,the density of the buried dielectric film 7 is increased byhigh-temperature annealing in a nitrogen or oxygen ambient.Planarization is then performed by chemical mechanical polishing (CMP)by using the silicon nitride film 4 as a stopper, thereby obtaining astructure shown in FIG. 3.

The silicon oxide film 7 (buried dielectric film) is etched by using amethod capable of etching with selectivity to the silicon nitride film4. This etching positions the upper surface of the silicon oxide film 7between the upper surface and bottom surface of the floating gateelectrode layer 3. In this embodiment, as shown in FIG. 4, the surfaceof the silicon oxide film 7 is etched away to a height corresponding toabout half the film thickness of the floating gate electrode layer 3. Astructure shown in FIG. 4 is obtained by removing the silicon nitridefilm 4 by a method having selectivity to the silicon oxide film 7.

As shown in FIG. 5, an interelectrode dielectric film 8 (seconddielectric layer) is formed on the lower layers having the structureshown in FIG. 4. The interelectrode dielectric film 8 is a multilayereddielectric film including three dielectric films 81 to 83. The structureshown in FIG. 5 is formed by the following procedure.

First, a silicon nitride film 81 (lower dielectric film) having athickness of 0.5 to 10 nm is formed by CVD on the lower layers havingthe structure shown in FIG. 4. Then, a silicon oxide film 82(intermediate dielectric film) having a thickness of 0.5 to 15 nm isformed on the silicon nitride film 81 by CVD. Finally, a silicon nitridefilm 83 (upper dielectric film) having a thickness of 0.5 to 10 nm isformed on the silicon oxide film 82 by CVD, thereby forming theinterelectrode dielectric film 8 shown in FIG. 5.

In addition, as shown in FIG. 6, a 10- to 200-nm-thick control gateelectrode layer 9 made of, e.g., polysilicon is formed on theinterelectrode dielectric film 8. The control gate electrode layer 9functions as a control electrode in the nonvolatile semiconductor memorydevice. A sectional structure shown in FIG. 6 is obtained by forming amask material 10 on the control gate electrode layer 9.

After that, the mask material 10 is coated with a resist (not shown),and the resist is patterned by pattern exposure. This resist is used asa mask to etch away the mask material 10, control gate electrode layer9, interelectrode dielectric film 8 (second dielectric layer), floatinggate electrode layer 3, and first dielectric layer 2 (this step is notshown).

The resist and mask material 10 are then removed to obtain a structureshown in FIG. 7, as a sectional view taken along a line A-A′ in FIG. 6and perpendicular to the drawing surface. Source and drain regions 20are formed by ion implantation in the surface of the substrate 1 as thebottom portions of the etched regions (isolation trenches) shown in FIG.7.

In this state, an oxidation process is performed in a steam ambient at750° C. for an oxidation time of 30 min. This forms interface oxidefilms as shown in FIG. 8. That is, a silicon oxide film 11 is formed onthe sidewall surfaces of the etched floating gate electrode layer 3, andon those portions of the interface, which continue from theabove-mentioned sidewall surfaces, between the floating gate electrodelayer 3 and interelectrode dielectric film 8 (i.e., the silicon nitridefilm 81). Also, a silicon oxide film 13 is formed on the sidewallsurfaces of the etched control gate electrode layer 9, and on thoseportions of the interface, which continue from the above-mentionedsidewall surfaces, between the control gate electrode layer 9 andinterelectrode dielectric film 8 (i.e., the silicon nitride film 83).

By performing the oxidation process under the oxidizing conditions witha high oxidizing power in the presence of steam as in this embodiment,it is possible to oxidize the floating gate electrode layer 3 from bothsides along the interface between the floating gate electrode layer 3and interelectrode dielectric film 8, and simultaneously oxidize thecontrol gate electrode layer 9 from both sides along the interfacebetween the control gate electrode layer 9 and interelectrode dielectricfilm 8. This rounds the corners along the gate width direction of thefloating gate electrode layer 3 and control gate electrode 9, and makesit possible to recover the damage caused by mixing of ions and the likeduring the etching. Consequently, the leakage current can be reduced.

In this case, the silicon oxide film 11 penetrates between the floatinggate electrode layer 3 and silicon nitride film 81 from both sides, andthe silicon oxide film 13 penetrates between the control gate electrodelayer 9 and silicon nitride film 83 from both sides. To effectivelyreduce the leakage current caused via the corners of the floating gateelectrode layer 3 and control gate electrode layer 9, the length ofpenetration of the silicon oxide films 11 and 13 measured in the gatelength direction from the sidewalls of the floating gate electrode layer3 and control gate electrode layer 9 is desirably 5% or more of the filmthickness of the interelectrode dielectric film 8.

On the other hand, from the viewpoint of the coupling ratio (C1/(C1+C2))defined by the capacitance (C1) of the interelectrode dielectric film 8and the capacitance (C2) of the tunnel dielectric film 2, the couplingratio decreases as the penetration length described above increases.This is so because when the penetration length increases, both thecontact area between the floating gate electrode layer 3 andinterelectrode dielectric film 8 and the contact area between thecontrol gate electrode layer 9 and interelectrode dielectric film 8reduce, and this decreases the capacitance of the interelectrodedielectric film 8.

To suppress the fluctuation from the desired coupling ratio to 5% orless, therefore, the penetration length is desirably 4% or less of thecell length, i.e., the width in the gate length direction of thefloating gate electrode layer 3 or control gate electrode layer 9.

Note that the oxidation process may also be performed not in the steamambient but by plasma oxidation at a temperature of about 400° C.

Subsequently, as shown in FIGS. 9, a 200- to 1,500-nm-thick burieddielectric film 12 (buried dielectric layer) for isolation made of asilicon oxide film or the like is formed and buried in theisolation-trenches. After that, a high-temperature annealing step isperformed in a nitrogen or oxygen ambient to increase the density of theburied dielectric film 12. Planarization is then performed by chemicalmechanical polishing (CMP) by using the control gate electrodes 9 asstoppers.

Consequently, as shown in FIG. 9, a silicon oxide film 11 is formed nearthe buried dielectric film 12 in the interface between the floating gateelectrode layer 3 and silicon nitride film 81, and a silicon oxide film13 is formed near the buried dielectric film 12 in the interface betweenthe control gate electrode layer 9 and silicon nitride film 83.

If no interface oxide films are formed and the corners along the gatewidth direction of the floating gate electrode layer 3 and control gateelectrode layer 9 are close to the right angle, an electric fieldconcentrates to these corners to allow a leakage current to readily flowthrough the interelectrode dielectric film 8. However, when the siliconoxide films 11 and 13 are formed as in this embodiment, the corners ofthe floating gate electrode layer 3 and control gate electrode layer 9can be rounded. Since this makes it possible to alleviate the fieldconcentration near the corners, the leakage current can be reduced.

FIG. 10 shows the current densities of leakage currents that flowthrough the interelectrode dielectric film when no interface oxide filmsare formed and interface oxide films are formed as in this embodiment.As shown in FIG. 10, the formation of the interface oxide films reducesthe leakage current.

In this embodiment, the interelectrode dielectric film 8 has thethree-layered structure including silicon nitride film-silicon oxidefilm-silicon nitride film (NON). However, the interelectrode dielectricfilm 8 is not limited to this structure. For example, the same effectsas in the above embodiment can be obtained by a silicon nitridefilm-silicon oxide film-silicon nitride film-silicon oxide film-siliconnitride film (NONON) five-layered structure in which the silicon oxidefilm as an intermediate dielectric film in the center of thethree-layered structure has an ONO structure including silicon oxidefilm-silicon nitride film-silicon oxide film. Since a silicon nitridefilm traps electric charge, this structure can further reduce theleakage current flowing through the interelectrode dielectric film.

Second Embodiment

Fabrication steps of a nonvolatile semiconductor memory device accordingto the second embodiment of the present invention will be explainedbelow.

In this embodiment, the structure shown in FIG. 7 is formed by the samesteps as in the first embodiment. This embodiment further ion-implantsphosphorus (P) in memory cell regions of the structure shown in FIG. 7in which source and drain regions 20 are already formed by ionimplantation. In this ion implantation, phosphorus ions may also beimplanted in, e.g., an oblique direction so as to be readily implantedinto silicon nitride films 81 and 83 from the sidewalls.

After that, an oxidation process is performed in an oxygen ambient at850° C. for an oxidation time of 30 min, thereby obtaining the samestructure as in the first embodiment shown in FIG. 8.

Oxidation performed after phosphorus is ion-implanted into the siliconnitride films 81 and 83 as in this embodiment promotes oxidation of thesilicon nitride films 81 and 83 that originally hardly oxidize. Thisaccelerates penetration in the gate length direction of a silicon oxidefilm 11 into the interface between a floating gate electrode layer 3 andinterelectrode dielectric film 8 (i.e., the silicon nitride film 81),and penetration in the gate length direction of a silicon oxide film 13into the interface between a control gate electrode layer 9 and theinterelectrode dielectric film 8 (i.e., the silicon nitride film 83).

This embodiment can also round the corners in the gate width directionof the floating gate electrode layer 3 and control gate electrode layer9, and recover the damage caused by mixing of ions and the like duringetching, thereby reducing the leakage current. Steps to FIG. 9 afterthat are the same as in the first embodiment.

To effectively reduce the leakage current caused via the corners of thefloating gate electrode layer 3 and control gate electrode layer 9, thelength of penetration of the silicon oxide films 11 and 13 measured fromthe sidewalls of the floating gate electrode layer 3 and control gateelectrode layer 9 is desirably 5% or more of the film thickness of theinterelectrode dielectric film 8, in this embodiment as well.

On the other hand, to suppress the fluctuation from the desired couplingratio to 5% or less, the penetration length is desirably 4% or less ofthe cell length, i.e., the width in the gate length direction of thefloating gate electrode layer 3 or control gate electrode layer 9.

Note that the oxidation process may also be performed not under theabove-mentioned conditions but by plasma oxidation at a temperature ofabout 400° C.

The interelectrode dielectric film 8 is not limited to the three-layeredstructure including silicon nitride film-silicon oxide film-siliconnitride film (NON) in this embodiment as well. For example, the sameeffects as in the above embodiment can be obtained by a silicon nitridefilm-silicon oxide film-silicon nitride film-silicon oxide film-siliconnitride film (NONON) five-layered structure in which the silicon oxidefilm as an intermediate dielectric film in the center of thethree-layered structure has an ONO structure including silicon oxidefilm-silicon nitride film-silicon oxide film. Since a silicon nitridefilm traps electric charge, this structure can further reduce theleakage current flowing through the interelectrode dielectric film.

Third Embodiment

Fabrication steps of a nonvolatile semiconductor memory device accordingto the third embodiment of the present invention will be explainedbelow.

This embodiment also forms the structure shown in FIG. 7 by the samesteps as in the first embodiment. In the structure shown in FIG. 7,however, this embodiment performs wet etching on silicon nitride films81 and 83 by using a phosphoric acid solution, thereby obtaining astructure shown in FIG. 11.

As shown in FIG. 11, this wet etching partially removes one or both ofthe silicon nitride films 81 and 83 in the gate length direction,thereby making the width in the gate length direction smaller than thatin the gate length direction of a floating gate electrode layer 3 orcontrol gate electrode layer 9.

After that, an oxidation process is performed in an oxygen ambient at850° C. for an oxidation time of 30 min. This oxidation process formsinterface oxide films as shown in FIG. 12. That is, a silicon oxide film11 is formed on the sidewall surfaces of the floating gate electrodelayer 3 that is etched by etching for forming isolation trenches, and onthose portions of the interface, which continue from the above-mentionedsidewall surfaces, between the floating gate electrode layer 3 and aninterelectrode dielectric film 8 (i.e., the silicon nitride film 81).Also, a silicon nitride film 13 is formed on the sidewall surfaces ofthe control gate electrode layer 9 that is similarly etched, and onthose portions of the interface, which continue from the above-mentionedsidewall surfaces, between the control gate electrode layer 9 andinterelectrode dielectric film 8 (i.e., the silicon nitride film 83).

Note that as shown in FIG. 12, the width of the removal of the siliconnitride films 81 and 83 by the wet etching described above is desirablylarger than the film thickness of the silicon oxide films 11 and 13respectively formed on the sidewall surfaces of the floating gateelectrode layer 3 and control gate electrode layer 9.

The floating gate electrode layer 3 and control gate electrode layer 9are exposed by etching the silicon nitride films 81 and 83 by using aphosphoric acid solution as in this embodiment. It is possible viaoxidation of the exposed surfaces to accelerate oxidation of thefloating gate electrode layer 3 from both sides along the interfacebetween the floating gate electrode layer 3 and interelectrodedielectric film 8 (silicon nitride film 81), and oxidation of thecontrol gate electrode layer 9 from both sides along the interfacebetween the control gate electrode layer 9 and interelectrode dielectricfilm 8 (silicon nitride film 83).

That is, it is possible to promote penetration in the gate lengthdirection of the silicon oxide film 11 in the interface between thefloating gate electrode layer 3 and silicon nitride film 81, andpenetration in the gate length direction of the silicon oxide film 13 inthe interface between the control gate electrode layer 9 and siliconnitride film 83.

Consequently, as shown in FIG. 12, the silicon oxide films 11 and 13penetrate to portions deeper than the sidewalls of the silicon nitridefilms 81 and 83 partially removed by wet etching.

This interface oxidation rounds the corners of the floating gateelectrode layer 3 and control gate electrode layer 9, and can alsorecover the damage caused by mixing of ions and the like during etching,thereby reducing the leakage current.

To effectively reduce the leakage current caused via the corners of thefloating gate electrode layer 3 and control gate electrode layer 9, thelength of penetration of the silicon oxide films 11 and 13 measured fromthe sidewalls of the floating gate electrode layer 3 and control gateelectrode layer 9 is desirably 5% or more of the film thickness of theinterelectrode dielectric film 8, in this embodiment as well.

On the other hand, to suppress the fluctuation from the desired couplingratio to 5% or less, the penetration length is desirably 4% or less ofthe cell length, i.e., the width in the gate length direction of thefloating gate electrode layer 3 or control gate electrode layer 9.

Note that the oxidation process may also be performed not under theabove-mentioned conditions but by plasma oxidation at a temperature ofabout 400° C.

Subsequently, as shown in FIGS. 13, a 200- to 1,500-nm-thick burieddielectric film 12 for isolation made of a silicon oxide film or thelike is formed and buried in the isolation trenches. After that, ahigh-temperature annealing step is performed in a nitrogen or oxygenambient to increase the density of the buried dielectric film 12.Planarization is then performed by chemical mechanical polishing (CMP)by using the control gate electrodes 9 as stoppers.

Consequently, as shown in FIG. 13, a silicon oxide film 11 is formednear the buried dielectric film 12 in the interface between the floatinggate electrode layer 3 and silicon nitride film 81, and a silicon oxidefilm 13 is formed near the buried dielectric film 12 in the interfacebetween the control gate electrode layer 9 and silicon nitride film 83.

It is conventionally difficult to recover the damage inflicted on thesidewalls of the silicon nitride films 81 and 83 by etching. However,this embodiment can remove the damaged portions that produce a leakagecurrent, by wet-etching the sidewalls of the silicon nitride films 81and 83. This can also reduce the leakage current.

The interelectrode dielectric film 8 is not limited to the three-layeredstructure including silicon nitride film-silicon oxide film-siliconnitride film (NON) in this embodiment as well. For example, the sameeffects as in the above embodiment can be obtained by a silicon nitridefilm-silicon oxide film-silicon nitride film-silicon oxide film-siliconnitride film (NONON) five-layered structure in which the silicon oxidefilm as an intermediate dielectric film in the center of thethree-layered structure has an ONO structure including silicon oxidefilm-silicon nitride film-silicon oxide film. Since a silicon nitridefilm traps electric charge, this structure can further reduce theleakage current flowing through the interelectrode dielectric film.

One aspect of the present invention can provide a nonvolatilesemiconductor memory device that reduces a leakage current flowingthrough an interelectrode dielectric film, particularly, aninterelectrode dielectric film having silicon nitride films in the upperand lower interfaces.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details and representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventiveconcept as defined by the appended claims and their equivalents.

1.-14. (canceled)
 15. A nonvolatile semiconductor memory devicefabrication method comprising: forming a first dielectric layer on amajor surface of a semiconductor substrate; forming a floating gateelectrode layer on the first dielectric layer; etching two side surfacesin a gate length direction of each of the floating gate electrode layerand the first dielectric layer; covering, with an dielectric film, thetwo side surfaces in the gate length direction of the first dielectriclayer and at least portions of the two side surfaces in the gate lengthdirection of the floating gate electrode layer, thereby forming a burieddielectric layer having an upper surface positioned between an uppersurface and a bottom surface of the floating gate electrode layer;forming a second dielectric layer on the floating gate electrode layerand the buried dielectric layer, comprising: forming a lower dielectricfilm mainly containing silicon and nitrogen; forming an intermediatedielectric film on the lower dielectric film; and forming an upperdielectric film mainly containing silicon and nitrogen on theintermediate dielectric film; forming a control gate electrode layer onthe second dielectric layer; etching two side surfaces in a gate widthdirection of each of the first dielectric layer, the floating gateelectrode layer, the second dielectric layer, and the control gateelectrode layer; and forming, by oxidation, a first silicon oxide filmis an interface between the floating gate electrode layer and the lowerdielectric film.
 16. A method according to claim 15, wherein a corner ofthe floating gate electrode layer, which is formed along the gate widthdirection and in contact with the first silicon oxide film is rounded.17. A method according to claim 15, wherein the intermediate dielectricfilm is a silicon oxide film.
 18. A method according to claim 15,wherein forming the intermediate dielectric film comprises: forming asilicon oxide film; forming an dielectric film mainly containing siliconand nitrogen on the silicon oxide film; and forming another siliconoxide film on the dielectric film mainly containing silicon andnitrogen.
 19. A method according to claim 15, further comprising, beforethe oxidation, wet-etching the lower dielectric film to make a width inthe gate length direction of the lower dielectric film smaller than awidth in the gate length direction of the floating gate electrode layer.20. A method according to claim 15, wherein the oxidation is one ofoxidation executed in one of a steam ambient and an oxygen ambient, andplasma oxidation.
 21. A nonvolatile semiconductor memory devicefabrication method comprising: forming a first dielectric layer on amajor surface of a semiconductor substrate; forming a floating gateelectrode layer on the first dielectric layer; etching two side surfacesin a gate length direction of each of the floating gate electrode layerand the first dielectric layer; covering, with an dielectric film, thetwo side surfaces in the gate length direction of the first dielectriclayer and at least portions of the two side surfaces in the gate lengthdirection of the floating gate electrode layer, thereby forming a burieddielectric layer having an upper surface positioned between an uppersurface and a bottom surface of the floating gate electrode layer;forming a second dielectric layer on the floating gate electrode layerand the buried dielectric layer, the forming the second dielectric layercomprising: forming a lower dielectric film mainly containing siliconand nitrogen; forming an intermediate dielectric film on the lowerdielectric film; and forming an upper dielectric film mainly containingsilicon and nitrogen on the intermediate dielectric film; forming acontrol gate electrode layer on the second dielectric layer; etching twoside surfaces in a gate width direction of each of the first dielectriclayer, the floating gate electrode layer, the second dielectric layer,and the control gate electrode layer; and forming, by oxidation, a firstsilicon oxide film in an interface between the control gate electrodelayer and the upper dielectric film.
 22. A method according to claim 21,wherein a corner of the control gate electrode layer, which is formedalong the gate width direction and in contact with the first siliconoxide film is rounded.
 23. A method according to claim 21, wherein theintermediate dielectric film is a silicon oxide film.
 24. A methodaccording to claim 21, wherein forming the intermediate dielectric filmcomprises: forming a silicon oxide film; forming an dielectric filmmainly containing silicon and nitrogen on the silicon oxide film; andforming another silicon oxide film on the dielectric film mainlycontaining silicon and nitrogen.
 25. A method according to claim 21,further comprising, before the oxidation, wet-etching the upperdielectric film to make a width in the gate length direction of theupper dielectric film smaller than a width in the gate length directionof the control gate electrode layer.
 26. A method according to claim 21,wherein the oxidation is one of oxidation executed in one of a steamambient and an oxygen ambient, and plasma oxidation.